Design of Parallel Prefix Tree Structure for CMOS Comparator

This paper proposes a comparator design using conventional digital CMOS cells featuring wide-range and high-speed operation. The Comparison is most basic arithmetic operation that determines whether one number is greater than, less than or equal to the other number. Our comparator uses a novel scalable parallel prefix structure that leverages the comparison outcome of the MSB, proceeding bitwise towards LSB only when the comparison bits are equal. This comparator is composed of locally interconnected CMOS gates with a maximum fan-in of five and fan-out of four, independent of comparator bandwidth. Comparator is most fundamental component that performs comparison operation. Comparison between modified and existing 8-bit binary comparator designs is calculated by simulation performed at 90nm technology in DSCH, Microwind Tool The main advantages of our proposed design are high speed and power efficiency, maintained over a wide range.